搜索资源列表
pcirtl
- 用verilog编写的pci——rtl级。-using Verilog prepared by the pci -- rtl level.
rs_decoder_31_19_6.tar
- Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1
rgb2yuv
- verilog编写，rtl风格，流水线设计，实现图像rgb格式到yuv格式的转换。
or1200
- or1200的内核以及一些参考文献，是Verilog的RTL级描述。
Camera_Interface_Verilog
- 该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating
lift_verilog
- 用verilog实现的电梯控制器，代码中有详细的注释说明，是学习rtl设计很好的资料-The elevator controller using verilog implementation, the code has detailed notes, is good datum to learn rtl design
ac97_latest.tar
- ac97的verilog实现，包含详细的代码实现以及仿真，非常可靠-ac97，verilog rtl
VHDLvsVerilog
- This document is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor
reset
- 这是个关于同步复位和异步复位问题的探讨，最后得出同步释放，异步复位的效果最好 文件中有编好的verilog文件工程，以及仿真结果和RTL分析图，分析的很详细-This is a synchronous reset and asynchronous reset on the issue of the conclusion that synchronous release, asynchronous reset of the best documents are programmed veril
8088verilog
- intel8088的verilog core ，完整的RTL-intel 8088 verilog core， all RTL
i2c
- I2C的RTL源码，verilog，验证过的-I2C verilog RTL
Full.adder
- Verilog的RTL级别全加器和测试平台，测试通过-Verilog RTL level full adder and test benck
GCD
- Verilog 最大公约数设计RTL级代码和芯片设计图-Verilog GCD Design and synthesis layout
Modelsim--script-usage
- modelsim是Mentor graphics公司推出的HDL代码仿真工具，也是业界最流行的HDL仿真工具之一。支持图形界面操作和脚本操作。常见的图形界面操作相对直观，但是由于重复性操作几率高、处理效率低、工程的非保存性，对于大规模的代码仿真不推荐使用；脚本操作完全可以克服以上的缺点，把常见的命令，比如库文件和RTL加载、仿真、波形显示等命令编辑成.do脚本文件，只需要让Modelsim运行.do文件即可以完成仿真，智能化程度高。本文重点介绍Modelsim常见命令的使用，以及如何使用.do
rtl
- Learn the code freely to provide everyone with learning and hope to help everyone. Thank you
8051 Verilog Code
- 8051 Core Verilog RTL code
AES128 Verilog Code
- AES128 Encryption/Decryption Verilog RTL Code
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving prop
RISC
- URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)
ppm编解码器
- 进行ppm编解码的verilog代码，RTL描述(Verilog code for ppm encoding and decoding, RTL descr iption)